1. Field of the Invention
The present invention relates to an information processing apparatus, communication method and storage medium that transfer and process data using a ring-shaped bus.
2. Description of the Related Art
There is a conventional method for achieving high-speed pipeline processing, whereby a sequence of data processing constituting the pipeline processing is divided into groups, the groups of data processing are assigned to a plurality of modules, and the plurality of modules are connected by a bus in the order of the flow of processing (Japanese Patent Laid-Open No. 5-081178). However, when modules are connected by a physical bus, it is difficult to change the order of pipeline processing, e.g. change processes A→B→C to processes A→C→B. Note that the above assignment is made to avoid overlapping of processes A, B and C.
In image processing, the efficiency of processing may be improved by changing the order of the sequence of processing. For example, in the case where an image is output to an output apparatus, if the number of pixels in the input image is greater than the number of pixels of the output apparatus, it would be efficient to process the image after reducing the number of pixels therein in the upstream process close to the start of processing. On the other hand, if the number of pixels in the input image is smaller than the number of pixels of the output apparatus, it is better to process the image having the small number of pixels without executing resolution conversion, and then increase the number of pixels in the image by executing resolution conversion in the downstream process immediately before the output.
In some cases, data defined in a certain space (e.g. an input device space) is processed after being converted into a standard space (e.g. a CIELAB color space), and the processed data is converted into another space (e.g. an output device space). In such cases, the space conversion units at the input side and the output side execute processing (one-dimensional LUT, matrix operation, three-dimensional LUT, etc.) in the reverse order. That is to say, if the order of processing can be changed, the input side and the output side may be able to share the same processing module. One way to enable a change in the processing order is to connect processing circuits by a ring-shaped bus (hereinafter referred to as a ring bus) (Japanese Patent Laid-Open No. 1-023340 and No. 2-283142).
However, in the case of a branch process where two processes A→B and A→C are simultaneously executed in pipeline processing composed of processes A→B→C, if a processing module at one side suspends a packet without processing the same, that processing module cannot be identified. This gives rise to the problem that the suspended packet cannot be deleted at a correct timing and is therefore stalled on the ring bus. Furthermore, should the suspended packet be deleted before data included in the suspended packet is processed by another processing module that is supposed to process that data, the subsequent packets cannot be processed. This gives rise to the problem that the ring bus ends up in a deadlock.
The present invention provides technology for executing a branch process without losing data in a data path control mechanism in which a plurality of processing units are connected by a ring-shaped bus.